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| CY7C1049CV33 512K x 8 Static RAM Features * High speed -- tAA = 10 ns * Low active power -- 324 mW (max.) * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1049CV33 is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Functional Description[1] The CY7C1049CV33 is a high-performance CMOS Static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Logic Block Diagram Pin Configuration SOJ Top View TSOP II Top View NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 ARRAY I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -8[2] 8 100 110 10 -10 10 90 100 10 -12 12 85 95 10 -15 15 80 90 10 Unit ns mA mA mA A 11 A 12 A 13 A14 A15 A16 A17 A18 Commercial Industrial Commercial / Industrial Notes: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. 2. Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05006 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised September 13, 2002 CY7C1049CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [3] DC Voltage Applied to Outputs in High-Z State[3].................................... -0.5V to VCC + 0.5V DC Input Voltage[3] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V .... -0.5V to +4.6V Electrical Characteristics Over the Operating Range Parameter Description Output HIGH Voltage VOH Output LOW Voltage VOL VIH Input HIGH Voltage VIL IIX IOZ ICC ISB1 Input LOW Voltage[3] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs Test Conditions VCC = Min.; IOH = -4.0 mA VCC = Min.,; IOL = 8.0 mA -8[2] -10 -12 -15 Min. Max. Min. Max. Min. Max. Min. Max. Unit 2.4 2.4 2.4 2.4 V 0.4 0.4 0.4 0.4 V V 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC + 0.3 + 0.3 + 0.3 + 0.3 -0.3 0.8 -0.3 0.8 -0.3 0.8 -0.3 0.8 V -1 +1 -1 +1 -1 +1 -1 +1 A -1 +1 -1 +1 -1 +1 -1 +1 A 100 110 40 90 100 40 85 95 40 80 90 40 mA mA mA GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., Comm'l f = fMAX = 1/tRC Ind'l Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Com'l/Ind'l Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 ISB2 10 10 10 10 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF AC Test Loads and Waveforms[5] 8-, 10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12-, 15-ns devices: Z = 50 3.3V R 317 30 pF* OUTPUT 30 pF R2 351 (a) High-Z characteristics: 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF (b) R 317 R2 351 Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05006 Rev. *B Page 2 of 7 CY7C1049CV33 AC Switching Characteristics[6] Over the Operating Range -8[2] Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE LOW to CE HIGH to High-Z[8, 9] 3 4 0 8 8 6 6 0 0 6 4 0 3 4 10 7 7 0 0 7 5 0 3 5 0 10 12 8 8 0 0 8 6 0 3 6 High-Z[8, 9] Low-Z[9] 0 4 3 5 0 12 15 10 10 0 0 10 7 0 3 7 3 8 4 0 5 3 6 0 15 1 8 8 3 10 5 0 6 3 7 1 10 10 3 12 6 0 7 1 12 12 1 15 15 3 15 7 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -10 Max. Min. -12 Max. Min. -15 Max. Unit CE LOW to Power-up CE HIGH to Power-down Cycle[10, 11] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[8, 9] Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. Document #: 38-05006 Rev. *B Page 3 of 7 CY7C1049CV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE DATA OUT Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. During this period the I/Os are in the output state and input signals should not be applied. tHD DATAIN VALID Document #: 38-05006 Rev. *B Page 4 of 7 CY7C1049CV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE LOW)[16] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 17 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H High-Z Data Out Data In High-Z I/O0-I/O7 Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1049CV33-10VC CY7C1049CV33-10ZC CY7C1049CV33-10VI CY7C1049CV33-10ZI 12 CY7C1049CV33-12VC CY7C1049CV33-12ZC CY7C1049CV33-12VI CY7C1049CV33-12ZI 15 CY7C1049CV33-15VC CY7C1049CV33-15ZC CY7C1049CV33-15VI CY7C1049CV33-15ZI Package Name V36 Z44 V36 Z44 V36 Z44 V36 Z44 V36 Z44 V36 Z44 Package Type 36-lead (400-Mil) Molded SOJ 44-pin TSOP II 36-lead (400-Mil) Molded SOJ 44-pin TSOP II 36-lead (400-Mil) Molded SOJ 44-pin TSOP II 36-lead (400-Mil) Molded SOJ 44-pin TSOP II 36-lead (400-Mil) Molded SOJ 44-pin TSOP II 36-lead (400-Mil) Molded SOJ 44-pin TSOP II Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Document #: 38-05006 Rev. *B Page 5 of 7 CY7C1049CV33 Package Diagrams 36-lead (400-mil) Molded SOJ V36 51-85090-*B 44-pin TSOP II Z44 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05006 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1049CV33 Document History Page Document Title: CY7C1049CV33 512K x 8 Static RAM Document Number: 38-05006 REV. ** *A *B ECN NO. 112569 114091 116479 Issue Date 03/06/02 04/25/02 09/16/02 Orig. of Change HGK DFP CEA New Data Sheet Changed Tpower unit from ns to s Add applications foot note to data sheet, page 1. Description of Change Document #: 38-05006 Rev. *B Page 7 of 7 |
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